Secure-IC provide Chip Security Protection IP Cores: Cryptographic algorithm IP such as AES, DES, 3-DES, ECC, RSA, SM2, SM3, SM4, SHA1, SHA2, SHA3, HMAC, countermeasure IP such as TRNG, CTR-DRBG RNG, Digital Sensor, Active Shield, PUF, Smart Monitor, Scrambled Bus, Memory Ciphering, Cyber CPU, Secure Clock, Secure Book, Secure Monitor, Secure JTAG, etc.
Physically Unclonable Functions
Loop PUF, not SRAM PUF, not Via PUF
TRL9 technology, deployed in ASIC (ST 65 nm, UMC 55 nm,ST 28 nm) and FPGA (Xilinx Virtex-5, 65 nm, SASEBO-GII)
Use cases: smart-meter, governmental component, crypto chip Stochastic model: to answer to SLA from the industry (e.g., reliability < 10-9, which cannot be guaranteed by trial and error, cf. MTBF and FIT: Failure-In-Time)
Standardization: ISO/IEC 20897 (4th WD), co-editors:Sylvain Guilley, Soshi Hamaguchi, Yousung Kang.
Working on PUF in the framework of KeyHAS (with ETRI)
Numerous publications:[CDGB12, CDG+13, CDL+13, CCD+14, RSGD16b, RSGD16a, LDKG16, DGNR16, FSH+16, KDLG16, KDSG17]
In cryptography, a key is used by ciphers to transform a plaintext into cipher text or cipher text into plaintext. The key is a sensitive information, therefore it must be generated by a true random source and it must be stored in a secure manner to avoid invasive and non-invasive attacks. The storage in a non-volatile memory represents a risk to retrieve the key as explained in [SSAQ02] and a deterministic generation makes the key vulnerable to attacks based on observation [LHA12].
PUF IP Core is a secret key generation system based on Physically Unclonable Functions (PUF). The secret key is extracted from PUF using its intrinsic properties. The key generated by the PUF is not readable but extracted using a group of helper-data. This distinctive feature allows a real protection against the reverse-engineering techniques compared to traditional methods that store the key in non-volatile memory.
· Uniqueness: each circuit has a unique signature.
· Steadiness: the response is always the same, whatever the noise and environment.
· Unclonable/Unpredictable/Randomness: the architecture is based on the global and local variations introduced during the manufacturing process.
· Tamper resistance: the PUF is robust against invasive and non-invasive attacks.
The figure above represents the PUF architecture. The PUF manager controls the PUF sources by giving various challenges. The measurements returned by the PUF sources are processed by the manager to generate the key.
Secure-IC provide various security IP cores as following list (keep updating).
| AES | Encryption, against Side-Channel Attacks |
| DES / 3-DES | Encryption, against Side-Channel Attacks |
| RSA | Encryption, against Side-Channel Attacks |
| ECC | Encryption, against Side-Channel Attacks |
| HASH (SHA-1/MD-5) | Encryption, against Side-Channel Attacks |
| SM2 | Encryption, against Side-Channel Attacks |
| SM3 | Encryption, against Side-Channel Attacks |
| SM4 | Encryption, against Side-Channel Attacks |
| TRNG | True Random Number Generator，Digital，against Harmonic EM Attacks |
| PUF | Digital, Anti Cloning/Counterfeiting，100% Unique, Random and Steady ID Generation |
| Digital Sensor | Anti Fault Injection Attacks, All-in-one Fault Injection Detector, Entirely Digital |
| Active Shield | Active Protection against Intrusive Attacks on ASIC, Anti Intrusive Hardware Modification. |
| Scrambled BUS | Encrypted Information to Prevent Probing on BUS, Anti Eavesdroping |
| Memory Ciphering | Memory Protection Against Reverse Engineering and Tampering |
| Secure Clock | Anti Synchronization to prevent efficient SCA and FIA |
| Secure JTAG | Authentication System to Secure the debugging channel on chip, Anti JTAG Violation |
| Secure Boot | Maximum security-enabling root-on-trust, Anti Firmware Tampering |
| Secure Monitor | Maximum security-enabling monitoring, Security policy bypass |
| CyberCPU CPU | CPU-agnostic Cyber Attack Sensor |
Current Products:Security IP: PUF
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