Secure-IC provide Chip Security Protection IP Cores: Cryptographic algorithm IP such as AES, DES, 3-DES, ECC, RSA, SM2, SM3, SM4, SHA1, SHA2, SHA3, HMAC, countermeasure IP such as TRNG, CTR-DRBG RNG, Digital Sensor, Active Shield, PUF, Smart Monitor, Scrambled Bus, Memory Ciphering, Cyber CPU, Secure Clock, Secure Book, Secure Monitor, Secure JTAG, etc.
CPU-agnostic Cyber Attack Sensor, Fully Digital. Work with all kings of other CPU. Not a CPU.
1. GLOBAL OVERVIEW
The CyberCPU comprises technologies for detecting cyber-attacks targeted to hijack and take the control of the CPU. Cyber-attacks covered by the CyberCPU technologies include the alteration of the program's control flow and memory corruption. CyberCPU technologies are available as portable security features to be integrated in a targeted CPU architecture or as a ready to use IP Core.
The security features provide anomalies detection capabilities that trigger alarms in the form of security exceptions.
Properties
• Hardware-enabled cyber-security
• Just-in-time cyber-attack detection
Availability
• Portable security features for other CPU architectures
• Ready to use CyberCPU IP core
Secure-IC provide various security IP cores as following list (keep updating).
| AES | Encryption, against Side-Channel Attacks |
| DES / 3-DES | Encryption, against Side-Channel Attacks |
| RSA | Encryption, against Side-Channel Attacks |
| ECC | Encryption, against Side-Channel Attacks |
| HASH (SHA-1/MD-5) | Encryption, against Side-Channel Attacks |
| SM2 | Encryption, against Side-Channel Attacks |
| SM3 | Encryption, against Side-Channel Attacks |
| SM4 | Encryption, against Side-Channel Attacks |
| TRNG | True Random Number Generator，Digital，against Harmonic EM Attacks |
| PUF | Digital, Anti Cloning/Counterfeiting，100% Unique, Random and Steady ID Generation |
| Digital Sensor | Anti Fault Injection Attacks, All-in-one Fault Injection Detector, Entirely Digital |
| Active Shield | Active Protection against Intrusive Attacks on ASIC, Anti Intrusive Hardware Modification. |
| Scrambled BUS | Encrypted Information to Prevent Probing on BUS, Anti Eavesdroping |
| Memory Ciphering | Memory Protection Against Reverse Engineering and Tampering |
| Secure Clock | Anti Synchronization to prevent efficient SCA and FIA |
| Secure JTAG | Authentication System to Secure the debugging channel on chip, Anti JTAG Violation |
| Secure Boot | Maximum security-enabling root-on-trust, Anti Firmware Tampering |
| Secure Monitor | Maximum security-enabling monitoring, Security policy bypass |
| CyberCPU CPU | CPU-agnostic Cyber Attack Sensor |
Current Products:Security IP: CyberCPU
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